1. Field of the Invention
The present invention relates to the field of thin-film transistors and more particularly to the field of thin-film transistor metallization.
2. Background Information
Amorphous silicon (a-Si) thin-film transistors (TFTs) are used in both display and imager applications. These field effect transistors (FETs) are primarily used in array devices in which the electro-optically active portion of the devices comprises many individual pixels the electro-optical state of which must be individually set or read in accordance with the display or imager nature of the device. As such, such TFTs are fabricated in large quantities, in small sizes and in substantial densities on the substrates for such systems. For optimum system operation, every one of the TFT's in the array should have identical characteristics. While absolutely identical characteristics are probably unobtainable, there is presently a substantial problem with excessive variations in TFT characteristics across an entire array and even more so across an entire wafer. In particular, because of processing variations, the thin-film transistors in one portion of an array may have significantly different characteristics than the thin-film transistors in another portion of the array. Such variations in characteristics unduly restrict the maximum operating characteristics of the array (speed, signal to noise ratio, sensitivity and so forth). A parameter in which variation across a wafer is common is the spacing between the source and drain electrodes of the TFTs. Such variations have a number of undesirable effects. A larger source-to-drain electrode spacing translates directly into a larger source-to-drain region spacing which in turn results in reduced off-state capacitance for the thin film transistor. Another effect of increased source-to-drain electrode spacing is a reduction in the current provided by the transistor in response to a given set of gate and source-to-drain voltages. This reduction in current can decrease the speed of a liquid crystal display or increase the noise in an imaging device. Consequently, there is a need for improved thin-film transistor structures and methods of processing them which reduce, minimize or eliminate significant variations in the source-to-drain-electrode spacing of thin-film transistors across an array with a consequent reduction in variations in capacitance and current output. It is normal practice in the thin film transistor art to employ wet etchants to etch the source/drain metallization because such wet etchants are available which are highly selective between the source/drain metallization and the immediately underlying amorphous silicon which comprises the semiconductor material of the thin-film transistor. This use of wet etchants makes it possible to completely remove the source/drain metallization from the channel region of the transistor's semiconductor material without significant etching of the semiconductor material itself. Unfortunately, use of wet etching limits the main source-to-drain-electrode spacing due to linewidth loss from undercutting. Still worse, because the undercutting of the photoresist by the etchant is non-uniform and uncontrollable, such spacings vary significantly from lot to lot and in different portions of the same array. A source/drain metallization structure which is photoresist defined with a three micron spacing can end up after completion of the wet etch with as much as a four or five micron spacing. Still worse, this spacing typically varies across a given array.
A layer of chromium or a layer of molybdenum is commonly used as the source/drain metallization for thin-film transistors because each of them makes good ohmic contact to n.sup.+ amorphous silicon. These metallizations are typically deposited by sputtering. A common wet etchant for molybdenum is known as PAWN (phosphoric acid, acetic acid, water and nitrite acid). Such wet etchants have the unfortunate characteristic for thin-film transistors of patterning molybdenum with vertical sidewalls. As is well known in the semiconductor art, vertical sidewalls make it substantially more difficult to successfully passivate a structure with a deposited layer such as silicon dioxide or silicon nitride as compared to the same structure with sloped sidewalls. Non-continuous passivation can cause damage to lower layers while etching subsequently deposited layers of material.
A plasma or reactive ion etch (RIE) process can provide the required uniform source/drain metal spacings since such processes can be anisotropic in nature. In applications where a large area needs to be patterned, as in the case of an 8".times.8" liquid crystal display, typical RIE edge to center clearing, commonly referred to as the "bull's eye effect", can result in excessive and non-uniform removal of the underlying material, which in this application is silicon. The "bull's eye effect" becomes worse with increases in the thickness of the material being etched, and with the size of the part being etched.
Due to the aforementioned problems, there is a need for: a) an improved thin film transistor structure and fabrication process which provides the ability to produce more uniform source/drain spacings across an entire array or structure, b) the ability to produce smaller spaces between the source and drain electrodes in the vicinity of the channel region of a thin film transistor, c) an etching process which produces a source/drain metallization with a sloped sidewall profile so that subsequently deposited layers can more successfully passivate that structure and d) an etch process which patterns the source/drain metal without excessive and non-uniform removal of the underlying material.